[RS6000] PR89271, gcc.target/powerpc/vsx-simode2.c

[RS6000] PR89271, gcc.target/powerpc/vsx-simode2.c

This patch makes a number of corrections to rs6000_register_move_cost,
adds a new register union class, GEN_OR_VSX_REGS, and adjusts insn
alternative costs to suit.

The patch initially just corrected register move cost when direct
moves are available, but that resulted in regressions.  Inspection of
those regressions showed ALL_REGS being used as the register allocno
class, which isn't ideal.  gcc/doc/tm.texi says: "You should define a
class for the union of two classes whenever some instruction allows
both classes".  Thus, define GEN_OR_VSX_REGS for the register
allocator.  (IRA wants to use the union of two register classes when
the costs of the classes are below memory cost, which happens more
often with the low direct move cost.)

As per https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89271#c11 we ought
to be returning the minimal cost for union classes.  That can be done
by rs6000_register_move_cost testing for vsx first, where the number
of regs for a given mode might be smaller than the same mode in gprs,
and changing the LINK_OR_CTR_REGS case to exclude SPEC_OR_GEN_REGS and
NON_FLOAT_REGS.

I removed the VECTOR_MEM_VSX_P test since that leads to silly results
for scalar mode moves between altivec and float when TARGET_VSX.  eg.
rs6000_register_move_cost:, ret=2, mode=DF, from=FLOAT_REGS, to=FLOAT_REGS
rs6000_register_move_cost:, ret=16, mode=DF, from=FLOAT_REGS, to=ALTIVEC_REGS
rs6000_register_move_cost:, ret=2, mode=DF, from=FLOAT_REGS, to=VSX_REGS

The patch also fixes wrong results for moves within and between any of
the non-gpr, non-vsx special reg classes.  The comment about "moving
between two similar registers is just one instruction" is false.  We
can't move lr to ctr directly, for example.  I believe the intent of
the "reg_classes_intersect_p (to, from)" was to cover moves within
float or altivec, so I moved that test inside the code handling vsx,
and made sure the intersection wasn't anything besides vsx by masking
off everything else.  Masking isn't strictly necessary at the moment,
but would be if we create a GEN_OR_ALTIVEC_REGS class some time in the
future.

TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS is needed for rs6000 in order
to fix the 20% cactus_adm spec regression when using GEN_OR_VSX_REGS
as an allocno class.  It is similar to the aarch64 version but without
any selection by regno mode if the best class is a union class.

	PR target/89271
	* config/rs6000/rs6000.h (enum reg_class, REG_CLASS_NAMES),
	(REG_CLASS_CONTENTS): Add GEN_OR_VSX_REGS class.
	* config/rs6000/rs6000.c (rs6000_register_move_cost): Correct
	cost for general <-> vsx when direct moves are available.
	Cost union classes at minimal cost for any reg in the class.
	Correct calculation for moves between vsx, float, and altivec.
	Don't return a low cost for moves between special regs.  Don't
	use hard coded register numbers.
	(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): Define.
	(rs6000_ira_change_pseudo_allocno_class): New function.
	* config/rs6000/rs6000.md (movsi_internal1, mov<mode>_internal),
	(movdi_internal32, movdi_internal64): Remove '*' from vsx register
	alternatives.
	(movsi_internal1): Don't disparage vector alternatives.
	(mov<mode>_internal): Likewise, excepting alternative that
	will be split.
	* config/rs6000/vsx.md (vsx_splat_<mode>_reg): Don't disparage
	we <- b alternative.

From-SVN: r271022