[AArch64] Pattern-match SVE extending loads
authorRichard Sandiford <richard.sandiford@arm.com>
Sat, 16 Nov 2019 11:11:47 +0000 (11:11 +0000)
committerRichard Sandiford <rsandifo@gcc.gnu.org>
Sat, 16 Nov 2019 11:11:47 +0000 (11:11 +0000)
commit217ccab8f46ca5b260319e7b71b421daec6d11c8
treea3ef07b19bc12a62c9612d4bf2d8179469013b49
parente58703e2c1b09d39714740e00933d32df965de32
[AArch64] Pattern-match SVE extending loads

This patch pattern-matches a partial SVE load followed by a sign or zero
extension into an extending load.  (The partial load is already an
extending load; we just don't rely on the upper bits of the elements.)

Nothing yet uses the extra LDFF1 and LDNF1 combinations, but it seemed
more consistent to provide them, since I needed to update the pattern
to use a predicated extension anyway.

2019-11-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-sve.md
(@aarch64_load_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>):
(@aarch64_load_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
(@aarch64_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>):
Combine into...
(@aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>):
...this new pattern, handling extension to partial modes as well
as full modes.  Describe the extension as a predicated rather than
unpredicated extension.
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>)
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>):
Combine into...
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>):
...this new pattern, handling extension to partial modes as well
as full modes.  Describe the extension as a predicated rather than
unpredicated extension.
* config/aarch64/aarch64-sve-builtins.cc
(function_expander::use_contiguous_load_insn): Add an extra
predicate for extending loads.
* config/aarch64/aarch64.c (aarch64_extending_load_p): New function.
(aarch64_sve_adjust_stmt_cost): Likewise.
(aarch64_add_stmt_cost): Use aarch64_sve_adjust_stmt_cost to adjust
the cost of SVE vector stmts.

gcc/testsuite/
* gcc.target/aarch64/sve/load_extend_1.c: New test.
* gcc.target/aarch64/sve/load_extend_2.c: Likewise.
* gcc.target/aarch64/sve/load_extend_3.c: Likewise.
* gcc.target/aarch64/sve/load_extend_4.c: Likewise.
* gcc.target/aarch64/sve/load_extend_5.c: Likewise.
* gcc.target/aarch64/sve/load_extend_6.c: Likewise.
* gcc.target/aarch64/sve/load_extend_7.c: Likewise.
* gcc.target/aarch64/sve/load_extend_8.c: Likewise.
* gcc.target/aarch64/sve/load_extend_9.c: Likewise.
* gcc.target/aarch64/sve/load_extend_10.c: Likewise.
* gcc.target/aarch64/sve/reduc_4.c: Add
--param aarch64-sve-compare-costs=0.

From-SVN: r278343
16 files changed:
gcc/ChangeLog
gcc/config/aarch64/aarch64-sve-builtins.cc
gcc/config/aarch64/aarch64-sve.md
gcc/config/aarch64/aarch64.c
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/sve/load_extend_1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_10.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_4.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_5.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_6.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_7.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_8.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/load_extend_9.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/sve/reduc_4.c