stop using MSR vfirst bit, move to SVSTATE bit 63 instead
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 15 Jul 2021 17:49:45 +0000 (18:49 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 15 Jul 2021 17:49:45 +0000 (18:49 +0100)
commit21b85c12ceed9ca0194a30c76384e0e61174dac8
treeaf72f1551c88529f2993b4fa956fa119cbad9c70
parentb7401880f096864d40220a17316daf6a8f3ffd61
stop using MSR vfirst bit, move to SVSTATE bit 63 instead
openpower/isa/simplev.mdwn
src/openpower/consts.py
src/openpower/decoder/isa/caller.py
src/openpower/decoder/isa/test_caller_setvl.py