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(parent: f53811a) | patch
radeonsi: align sdma byte count to dw
authorPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tue, 15 Oct 2019 13:19:22 +0000 (15:19 +0200)
committerPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Wed, 30 Oct 2019 17:03:14 +0000 (18:03 +0100)
commit21b9a6b59019fe232beb8e82fc0eb231e56df268
tree7961294d2281262d9a76264f45f91a9e57e3ef9ctree
parentf53811aeace20530a502ea1ead3d4d2230dc1945commit | diff
radeonsi: align sdma byte count to dw

If src/dst addresses are dw aligned and size is > 4 then we align
byte count to dw as well.

PAL implementation works like this.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeonsi/cik_sdma.c diff | blob | history