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(parent: 5a9ad05) | patch
add VERSA-ECP5 images, rename FPGA page
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 3 Nov 2020 13:29:07 +0000 (13:29 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 3 Nov 2020 13:29:07 +0000 (13:29 +0000)
commit21f6eeb945ba2e913723832bafb6f7dbf18b7bab
tree43377d5292583be4eaba4ee0e197254977628109tree
parent5a9ad05a05a8c610beafff175a5bd38234084861commit | diff
add VERSA-ECP5 images, rename FPGA page
HDL_workflow/2020-11-03_13-22.png [new file with mode: 0644] blob
HDL_workflow/2020-11-03_13-25.png [new file with mode: 0644] blob
HDL_workflow/ECP5_FPGA.mdwn [new file with mode: 0644] blob
HDL_workflow/fpga.mdwn [deleted file] blob | history
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