Merge pull request #907 from YosysHQ/clifford/fix906
authorClifford Wolf <clifford@clifford.at>
Fri, 29 Mar 2019 23:09:42 +0000 (00:09 +0100)
committerGitHub <noreply@github.com>
Fri, 29 Mar 2019 23:09:42 +0000 (00:09 +0100)
commit22035c20ff071ec5c30990258850ecf97de5d5b3
tree35cd5485c70c17e93426d54a104018bae90ed924
parent32bd0f22ec93202e67395901cdc64c20df7f0da7
parent584d2030bf53c703febe8fda9cae73c72416c6cc
Merge pull request #907 from YosysHQ/clifford/fix906

Build Verilog parser with -DYYMAXDEPTH=100000