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(parent: 8c1be04) | patch
ARM: Warn about and ignore accesses to DCCISW.
authorGabe Black <gblack@eecs.umich.edu>
Wed, 2 Jun 2010 17:58:08 +0000 (12:58 -0500)
committerGabe Black <gblack@eecs.umich.edu>
Wed, 2 Jun 2010 17:58:08 +0000 (12:58 -0500)
commit221e0ac5234b60283753af5d7173199085ededa6
treea27f0acb5209f6a1d777e7b6ee22dca541856840tree
parent8c1be04af62a333cff54aa5f349e8bb9e203f267commit | diff
ARM: Warn about and ignore accesses to DCCISW.

This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.
src/arch/arm/isa/formats/misc.isa diff | blob | history
src/arch/arm/miscregs.hh diff | blob | history