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(parent: 1e1d5e2) | patch
arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 26 Aug 2019 08:55:19 +0000 (09:55 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 6 Sep 2019 20:00:34 +0000 (20:00 +0000)
commit22273000d0cd8b695c4dea9613c649f764ed94ea
tree12bb8ae66fb688e4b3a0663e55912d5dd579e9cctree
parent1e1d5e247ecc55dc3d92875ca5ec6ae70879d8c1commit | diff
arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking

Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/miscregs.cc diff | blob | history
src/dev/arm/gic_v3_cpu_interface.cc diff | blob | history