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(parent: effc41f) | patch
back.rtlil: emit dummy logic to work around Verilog deficiencies.
authorwhitequark <cz@m-labs.hk>
Sun, 23 Dec 2018 10:14:05 +0000 (10:14 +0000)
committerwhitequark <cz@m-labs.hk>
Sun, 23 Dec 2018 10:14:42 +0000 (10:14 +0000)
commit2297fbee4e100eec1ab6ce09f63217534b8b55e3
tree827c19b64c7da1a4a22cf2a922c6cdc683f773a1tree
parenteffc41f14003a86481f383d00a9009135f59156ecommit | diff
back.rtlil: emit dummy logic to work around Verilog deficiencies.
nmigen/back/rtlil.py diff | blob | history