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(parent: 901bed5) | patch
isl/drm: Map HiZ and CCS tilings to Y
authorNanley Chery <nanley.g.chery@intel.com>
Wed, 27 Mar 2019 21:40:58 +0000 (14:40 -0700)
committerNanley Chery <nanley.g.chery@intel.com>
Mon, 28 Oct 2019 17:47:05 +0000 (10:47 -0700)
commit22be1447bb46b4dc63fbc2cfc696c01a0f90ab0e
tree25ea20b659f8f0941ce9fd272f7c35aa97fa7b57tree
parent901bed51227b1d3a186891068f29623b757ff2f2commit | diff
isl/drm: Map HiZ and CCS tilings to Y

In the function which translates ISL tilings to i915 tilings, map ISL's
HiZ and CCS tilings to Y instead of NONE (linear). The HW docs describe
HiZ and pre-Gen12 CCS surfaces as being Y-tiled in memory.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
src/intel/isl/isl_drm.c diff | blob | history