intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4
authorPohjolainen, Topi <topi.pohjolainen@gmail.com>
Wed, 3 May 2017 09:22:50 +0000 (12:22 +0300)
committerJason Ekstrand <jason.ekstrand@intel.com>
Wed, 17 May 2017 00:04:26 +0000 (17:04 -0700)
commit236f17a9f73935db6cddafd91e53a5fae34aae6e
treeb62cf42de3ddde56f98f282428529f7a5bc83137
parentdafc2f1887e192376a176bbd2bb346ad48fc13ae
intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4

The reasoning Chad gave in the comment for choosing a valign of 4 is
entirely bunk.  The fact that you have to multiply pitch by 2 is
completely unrelated to the halign/valign parameters used for texture
layout.  (Not completely unrelated.  W-tiling is just Y-tiling with a
bit of extra swizzling which turns 8x8 W-tiled chunks into 16x4 y-tiled
chunks so it makes everything easier if miplevels are always aligned to
8x8.)  The fact that RENDER_SURFACE_STATE::SurfaceVerticalAlignmet
doesn't have a VALIGN_8 option doesn't matter since this is gen7 and you
can't do stencil texturing anyway.

v2 (Jason Ekstrand):
 - Delete most of Chad's comment and add a more descriptive commit
   message.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
src/intel/isl/isl_gen7.c