re PR middle-end/60102 (powerpc fp-bit ices at dwf_regno)

re PR middle-end/60102 (powerpc fp-bit ices at dwf_regno)

	PR target/60102

[libgcc]
2014-07-31  Rohit  <rohitarulraj@freescale.com>
	* config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update
	  based on change in SPE high register numbers and 3 HTM registers.

[gcc]
2014-07-31  Rohit  <rohitarulraj@freescale.com>
	* config/rs6000/rs6000.c
	  (rs6000_reg_names) : Add SPE high register names.
	  (alt_reg_names) : Likewise.
	  (rs6000_dwarf_register_span) : For SPE high registers, replace
	  dwarf register numbers with GCC hard register numbers.
	  (rs6000_init_dwarf_reg_sizes_extra) : Likewise.
	  (rs6000_dbx_register_number): For SPE high registers, return dwarf
	  register number for the corresponding GCC hard register number.

	* config/rs6000/rs6000.h
	  (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard
	  register numbers for SPE high registers.
	  (DWARF_FRAME_REGISTERS) :  Likewise.
	  (DWARF_REG_TO_UNWIND_COLUMN) : Likewise.
	  (DWARF_FRAME_REGNUM) : Likewise.
	  (FIXED_REGISTERS) : Likewise.
	  (CALL_USED_REGISTERS) : Likewise.
	  (CALL_REALLY_USED_REGISTERS) : Likewise.
	  (REG_ALLOC_ORDER) : Likewise.
	  (enum reg_class) : Likewise.
	  (REG_CLASS_NAMES) : Likewise.
	  (REG_CLASS_CONTENTS) : Likewise.
	  (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers.

	* gcc.target/powerpc/pr60102.c: New testcase.

From-SVN: r213596