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(parent: 0d2c33f) | patch
verilog: default to input in sv mode if task/func has no dir ...
authorEddie Hung <eddie@fpgeh.com>
Wed, 13 May 2020 20:33:37 +0000 (13:33 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 13 May 2020 20:33:37 +0000 (13:33 -0700)
commit237962debd9fcb7e9fb45f53bc8a53f0c34d9888
treebac83bb1902f53e924d3f5d441f5de8e225a3f0ctree
parent0d2c33f9f4f8ca1bb507e3e688e0c7d372f0247bcommit | diff
verilog: default to input in sv mode if task/func has no dir ...

otherwise error
frontends/verilog/verilog_parser.y diff | blob | history