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(parent: 7d91dd5) | patch
back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
authorwhitequark <whitequark@whitequark.org>
Fri, 14 Dec 2018 10:57:13 +0000 (10:57 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 14 Dec 2018 10:57:13 +0000 (10:57 +0000)
commit240a40c2c2f8d6f1dea8ebbf2b2e601da50e8ec4
tree97793b9a2064bdc0be1ad76d74f02248ddf3b87etree
parent7d91dd56c809ee346085569b5548f2344479fbb7commit | diff
back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
nmigen/back/pysim.py diff | blob | history