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(parent: b872f02) | patch
arch-riscv: Fix disassembling of CSR instructions
authorIan Jiang <ianjiang.ict@gmail.com>
Tue, 18 Aug 2020 09:19:36 +0000 (17:19 +0800)
committerIan Jiang <ianjiang.ict@gmail.com>
Wed, 19 Aug 2020 05:03:46 +0000 (05:03 +0000)
commit243e240ee3823d6124dd30ae46671da8311c6b9a
treec1d8ece4ce7bddcb95889b1f6af46dc352528d0ctree
parentb872f02ab12ea3ea2054f3742901fecb78752205commit | diff
arch-riscv: Fix disassembling of CSR instructions

The correct formats of CSR instructions are:
- mnemonic rd, csr, rs1
- mnemonic rd, csr, uimm

This patch fixes the problem.

Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32814
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/insts/standard.cc diff | blob | history