Updated Verilog documentation
authorZipCPU <dgisselq@ieee.org>
Wed, 22 May 2019 00:55:46 +0000 (20:55 -0400)
committerZipCPU <dgisselq@ieee.org>
Wed, 22 May 2019 00:55:46 +0000 (20:55 -0400)
commit2462855e0fed6b43666df07f5e94e224c74d2efb
tree6f540ce63e7ff42bc17cd5263d6c8d0682eed6a2
parentf087a71f499f77970e43805fa48df7465aeeed6c
Updated Verilog documentation
docs/source/verilog.rst