mem: Cleanup flow for uncacheable accesses
authorAndreas Hansson <andreas.hansson@arm.com>
Fri, 27 Mar 2015 08:56:01 +0000 (04:56 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Fri, 27 Mar 2015 08:56:01 +0000 (04:56 -0400)
commit24763c21775aed939228b1c8f048f8f7982de91c
treebaf9be0d8d0cdbb96e0154a6d0d61be8250a0abf
parenta7a1e6004a0d2508913277b5c60d245fdcad2681
mem: Cleanup flow for uncacheable accesses

This patch simplifies the code dealing with uncacheable timing
accesses, aiming to align it with the existing miss handling. Similar
to what we do in atomic, a timing request now goes through
Cache::access (where the block is also flushed), and then proceeds to
ignore any existing MSHR for the block in question. This unifies the
flow for cacheable and uncacheable accesses, and for atomic and timing.
src/mem/cache/cache_impl.hh