arch,cpu: Add vector predicate registers
authorGiacomo Gabrielli <giacomo.gabrielli@arm.com>
Tue, 16 Oct 2018 15:04:08 +0000 (16:04 +0100)
committerGiacomo Gabrielli <giacomo.gabrielli@arm.com>
Wed, 30 Jan 2019 16:57:54 +0000 (16:57 +0000)
commit25474167e5b247d1b91fbf802c5b396a63ae705e
treeb509597b23d792734f55c33b8125eebfbd9cd3a5
parentc6f5db8743f19b02a38146d9cf2a829883387008
arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
50 files changed:
src/arch/SConscript
src/arch/alpha/isa.hh
src/arch/alpha/registers.hh
src/arch/arm/isa.hh
src/arch/arm/registers.hh
src/arch/generic/vec_pred_reg.hh [new file with mode: 0644]
src/arch/generic/vec_reg.hh
src/arch/isa_parser.py
src/arch/mips/isa.hh
src/arch/mips/registers.hh
src/arch/null/registers.hh
src/arch/power/isa.hh
src/arch/power/registers.hh
src/arch/riscv/isa.hh
src/arch/riscv/registers.hh
src/arch/sparc/isa.hh
src/arch/sparc/registers.hh
src/arch/x86/isa.hh
src/arch/x86/registers.hh
src/cpu/base_dyn_inst.hh
src/cpu/checker/cpu.hh
src/cpu/checker/thread_context.hh
src/cpu/exec_context.hh
src/cpu/inst_res.hh
src/cpu/minor/exec_context.hh
src/cpu/minor/scoreboard.cc
src/cpu/minor/scoreboard.hh
src/cpu/o3/O3CPU.py
src/cpu/o3/comm.hh
src/cpu/o3/cpu.cc
src/cpu/o3/cpu.hh
src/cpu/o3/dyn_inst.hh
src/cpu/o3/free_list.hh
src/cpu/o3/inst_queue_impl.hh
src/cpu/o3/regfile.cc
src/cpu/o3/regfile.hh
src/cpu/o3/rename.hh
src/cpu/o3/rename_impl.hh
src/cpu/o3/rename_map.cc
src/cpu/o3/rename_map.hh
src/cpu/o3/thread_context.hh
src/cpu/o3/thread_context_impl.hh
src/cpu/reg_class.cc
src/cpu/reg_class.hh
src/cpu/simple/exec_context.hh
src/cpu/simple_thread.hh
src/cpu/static_inst.hh
src/cpu/thread_context.cc
src/cpu/thread_context.hh
src/sim/insttracer.hh