soc/cores/clock: add Xilinx Ultrascale PLL/MMCM
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 8 Jan 2019 12:19:49 +0000 (13:19 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 8 Jan 2019 12:21:53 +0000 (13:21 +0100)
commit2581a00380fe426adb148a97a2ae2ae01f248656
tree2420509a95b37ac9b7c80340fdb7e3eaa7450e8c
parent68e1dfca2880ebcbbd899116c824bcd8471e34a4
soc/cores/clock: add Xilinx Ultrascale PLL/MMCM
litex/soc/cores/clock.py