Fixed "abc" pass for clk and enable signals driven by logic
authorClifford Wolf <clifford@clifford.at>
Sun, 21 Dec 2014 10:13:25 +0000 (11:13 +0100)
committerClifford Wolf <clifford@clifford.at>
Sun, 21 Dec 2014 10:13:25 +0000 (11:13 +0100)
commit25844b5683ab0d9a8ba5f4ee01bb5a601a1c8d24
treebcf74632976a66afb3a0c43a291d63e89726b9e7
parentf7b323196fbd1c2f35ab034b33f9617f7428cf31
Fixed "abc" pass for clk and enable signals driven by logic
passes/abc/abc.cc