arch-riscv: Fix disassembling of immediate for c.lui instruction
authorIan Jiang <ianjiang.ict@gmail.com>
Tue, 26 Nov 2019 03:35:07 +0000 (11:35 +0800)
committerIan Jiang <ianjiang.ict@gmail.com>
Sun, 1 Dec 2019 01:48:24 +0000 (01:48 +0000)
commit258c04fc3fc7e69d9b6885776c0184515154675e
tree98f0cb9a191f912de86ebe428831b80d61c08666
parentbcf041f257623e5c9e77d35b7531bae59edc0423
arch-riscv: Fix disassembling of immediate for c.lui instruction

For compressed instruction c.lui, the 6-bit immediate is left-shifted by 12
bits in decoding. While the original Gem5 gives the left-shifted value
directly in disassembly.
This patch fixes the problem by adding a new template CILuiExecute to
resume the immediate before outputting it in disassembly.
Note: The immediate is sign-extended to 20-bit to be compatible with GCC.

Change-Id: If73f72d3e8f85a8b10ce7a323379d8ad6c4c3085
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22567
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/isa/formats/compressed.isa
src/arch/riscv/isa/formats/standard.isa