Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
authorClifford Wolf <clifford@clifford.at>
Wed, 23 Jul 2014 07:00:16 +0000 (09:00 +0200)
committerClifford Wolf <clifford@clifford.at>
Wed, 23 Jul 2014 07:34:47 +0000 (09:34 +0200)
commit260c19ec5a3adb292158658dd69a352b9325ab64
treea5ee152f61ce7952afc7cc7ffaaef66b98511c3a
parentc61467a32c4bd3ec4b9e0cb6d36d602f0e4dea81
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
kernel/rtlil.cc
kernel/rtlil.h
passes/abc/abc.cc
passes/sat/share.cc