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(parent: 55d143a) | patch
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Thu, 29 Nov 2012 21:59:54 +0000 (22:59 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Thu, 29 Nov 2012 21:59:54 +0000 (22:59 +0100)
commit261166d92b06a96b473b4434a68f7dc6cde77b7e
tree5d4f86345484317573119284e1526d2a3b95ee3etree
parent55d143a454d76ba52363757ba41772b9b9c30389commit | diff
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)

See http://jandecaluwe.com/hdldesign/counting.html
migen/fhdl/verilog.py diff | blob | history