Add DDRSoC simulation
authorJean THOMAS <git0@pub.jeanthomas.me>
Fri, 26 Jun 2020 13:20:34 +0000 (15:20 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Fri, 26 Jun 2020 13:20:34 +0000 (15:20 +0200)
commit26c7b2f78616585f74a62fa2fb2c712c20a142a0
tree2f6201975df4f96cccb2465651ca1b2ee0beed66
parent7b380a3e4a3ae6a2c593fddb3938ae7f3829a620
Add DDRSoC simulation
gram/simulation/icarusecpix5platform.py [new file with mode: 0644]
gram/simulation/runsimsoc.sh [new file with mode: 0755]
gram/simulation/simsoc.py [new file with mode: 0644]
gram/simulation/uartbridge.py [new file with mode: 0644]