verilog: ignore variable property in combinatorial block
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 21 Dec 2011 22:00:36 +0000 (23:00 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 21 Dec 2011 22:00:36 +0000 (23:00 +0100)
commit26e0b817e8d491d709a8162eaf5276840d3edcc6
treef93117f3c262081cdbf8399dcde5b25a562fb01f
parent7456195775e9477a4eebfb3419f7f3b76fe97bd5
verilog: ignore variable property in combinatorial block
migen/fhdl/verilog.py