Fix for A_WIDTH == 2 but B_WIDTH==3
authorEddie Hung <eddie@fpgeh.com>
Tue, 23 Apr 2019 00:58:28 +0000 (17:58 -0700)
committerEddie Hung <eddie@fpgeh.com>
Tue, 23 Apr 2019 00:58:28 +0000 (17:58 -0700)
commit26e461f47da12b79e5b6682f692d81e2721ca0c0
treea1d62329e21aa28744ea1450e37419985101653c
parent1fa2c36fbd98ff8d748a70c4cb352fa1c6070dae
Fix for A_WIDTH == 2 but B_WIDTH==3
techlibs/xilinx/cells_map.v