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(parent: 98afe2b) | patch
verilog: strip leading and trailing spaces in macro args
authorZachary Snow <zach@zachjs.com>
Thu, 28 Jan 2021 16:26:21 +0000 (11:26 -0500)
committerZachary Snow <zach@zachjs.com>
Thu, 28 Jan 2021 16:26:35 +0000 (11:26 -0500)
commit27257a419fe94e10f24eea916c56821e22e43cc5
treee4f30ff6b441acbe2e07a2cc1785a2743081866dtree
parent98afe2b7589181c39281a6c58540f6756395e1d9commit | diff
verilog: strip leading and trailing spaces in macro args
frontends/verilog/preproc.cc diff | blob | history
tests/simple/macro_arg_surrounding_spaces.v [new file with mode: 0644] blob