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(parent: 7e8f7f4) | patch
Add new tests for Anlogic architecture
authorSergeyDegtyar <sndegtyar@gmail.com>
Mon, 23 Sep 2019 09:12:02 +0000 (12:12 +0300)
committerSergeyDegtyar <sndegtyar@gmail.com>
Mon, 23 Sep 2019 09:12:02 +0000 (12:12 +0300)
commit27377c46634263beb5f8c28cb34b0c87ed6e9525
tree45891fbd7f4486d0f90486cca0e42a74b84d8da1tree
parent7e8f7f4c59c96897159d32771d0c7179c5474281commit | diff
Add new tests for Anlogic architecture

Problems/questions:
- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
- Internal cell type $_TBUF_  is present.
23 files changed:
Makefile diff | blob | history
tests/anlogic/.gitignore [new file with mode: 0644] blob
tests/anlogic/add_sub.v [new file with mode: 0644] blob
tests/anlogic/add_sub.ys [new file with mode: 0644] blob
tests/anlogic/alu.v [new file with mode: 0644] blob
tests/anlogic/alu.ys [new file with mode: 0644] blob
tests/anlogic/counter.v [new file with mode: 0644] blob
tests/anlogic/counter.ys [new file with mode: 0644] blob
tests/anlogic/dffs.v [new file with mode: 0644] blob
tests/anlogic/dffs.ys [new file with mode: 0644] blob
tests/anlogic/fsm.v [new file with mode: 0644] blob
tests/anlogic/fsm.ys [new file with mode: 0644] blob
tests/anlogic/latches.v [new file with mode: 0644] blob
tests/anlogic/latches.ys [new file with mode: 0644] blob
tests/anlogic/memory.v [new file with mode: 0644] blob
tests/anlogic/memory.ys [new file with mode: 0644] blob
tests/anlogic/mux.v [new file with mode: 0644] blob
tests/anlogic/mux.ys [new file with mode: 0644] blob
tests/anlogic/run-test.sh [new file with mode: 0755] blob
tests/anlogic/shifter.v [new file with mode: 0644] blob
tests/anlogic/shifter.ys [new file with mode: 0644] blob
tests/anlogic/tribuf.v [new file with mode: 0644] blob
tests/anlogic/tribuf.ys [new file with mode: 0644] blob