dev: Cache the cacheLineSize in the DMA read FIFO.
authorGabe Black <gabe.black@gmail.com>
Sat, 5 Dec 2020 01:43:19 +0000 (17:43 -0800)
committerGabe Black <gabe.black@gmail.com>
Tue, 5 Jan 2021 02:09:25 +0000 (02:09 +0000)
commit27a41d6ef6de9ebf6db6ce256690307afbf165fa
tree68bddbbf4773e0010a469c83bd12762e38824f03
parent9e97dbe8c8a77643197b28737f47d9ef64d8bb17
dev: Cache the cacheLineSize in the DMA read FIFO.

This is a minor simplification which decouples the FIFO from the system
object at run time, although it does need to read the cache line size
out at construction time.

Change-Id: I57d96a676b9604663b6c9ed7c662640f507c5305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38482
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/dev/dma_device.cc
src/dev/dma_device.hh