Added support for "upto" wires to Verilog front- and back-end
authorClifford Wolf <clifford@clifford.at>
Mon, 28 Jul 2014 12:25:03 +0000 (14:25 +0200)
committerClifford Wolf <clifford@clifford.at>
Mon, 28 Jul 2014 12:25:03 +0000 (14:25 +0200)
commit27a872d1e7041be4894bc643a420587ff5894125
tree430d0411eaa4c4f6893576e2179d2eee93726def
parent3c45277ee0f5822181c6058f679de632f834e7d2
Added support for "upto" wires to Verilog front- and back-end
backends/verilog/verilog_backend.cc
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc
tests/simple/partsel.v