hdl.ast: add Value.{as_signed,as_unsigned}.
authorwhitequark <whitequark@whitequark.org>
Thu, 6 Feb 2020 18:27:55 +0000 (18:27 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 6 Feb 2020 18:27:55 +0000 (18:27 +0000)
commit27b47faf169908e6e5acdc4588b4caf58582e69d
tree374674b727bd3dd5ec9575e2bdcc9293e4a99f55
parent9301e31b69a7c37c42f33e6cba5f3f37bc97402f
hdl.ast: add Value.{as_signed,as_unsigned}.

Before this commit, there was no way to do so besides creating and
assigning an intermediate signal, which could not be extracted into
a helper function due to Module statefulness.

Fixes #292.
nmigen/back/pysim.py
nmigen/back/rtlil.py
nmigen/hdl/ast.py
nmigen/test/test_hdl_ast.py
nmigen/test/test_sim.py