projects / yosys.git / commit
| author | Clifford Wolf <clifford@clifford.at> | |
| Sun, 15 Sep 2013 09:52:57 +0000 (11:52 +0200) | ||
| committer | Clifford Wolf <clifford@clifford.at> | |
| Sun, 15 Sep 2013 09:52:57 +0000 (11:52 +0200) | ||
| commit | 288ba9618af9c5ba9db1131955c92d59166d120d | |
| tree | d65852d388355322a9e7166ba0b0661e24eb220e | tree |
| parent | 647c23b7b7e3a72fc64d9b1ad07dacd590865898 | commit | diff |
| Makefile | diff | blob | history | |
| manual/CHAPTER_CellLib.tex | diff | blob | history | |
| manual/CHAPTER_Techmap.tex | diff | blob | history | |
| passes/techmap/Makefile.inc | diff | blob | history | |
| techlibs/Makefile.inc | [deleted file] | blob | history |
| techlibs/blackbox.sed | [deleted file] | blob | history |
| techlibs/common/Makefile.inc | [new file with mode: 0644] | blob |
| techlibs/common/blackbox.sed | [new file with mode: 0644] | blob |
| techlibs/common/simlib.v | [new file with mode: 0644] | blob |
| techlibs/common/stdcells.v | [new file with mode: 0644] | blob |
| techlibs/common/stdcells_sim.v | [new file with mode: 0644] | blob |
| techlibs/simlib.v | [deleted file] | blob | history |
| techlibs/stdcells.v | [deleted file] | blob | history |
| techlibs/stdcells_sim.v | [deleted file] | blob | history |
| tests/i2c_bench/run-test.sh | diff | blob | history | |
| tests/tools/autotest.sh | diff | blob | history | |
| tests/tools/rtlview.sh | diff | blob | history |