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(parent: ccb512e) | patch
config: Add XOR hashing to the DRAM channel interleaving
authorAndreas Hansson <andreas.hansson@arm.com>
Tue, 3 Feb 2015 19:25:55 +0000 (14:25 -0500)
committerAndreas Hansson <andreas.hansson@arm.com>
Tue, 3 Feb 2015 19:25:55 +0000 (14:25 -0500)
commit28a7cea2b3208e3f01cada58dab0be656dfb85fd
tree93cb86af27efdd329847afae65fc2c548563057ctree
parentccb512ecc1b4224ef68f5cb76f59c3fd36a59c63commit | diff
config: Add XOR hashing to the DRAM channel interleaving

This patch uses the recently added XOR hashing capabilities for the
DRAM channel interleaving. This avoids channel biasing due to strided
access patterns.
configs/common/MemConfig.py diff | blob | history