fhdl/verilog: add flag to produce ASIC-friendly output
authorGuy Hutchison <ghutchis@gmail.com>
Tue, 21 Apr 2015 01:51:39 +0000 (09:51 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Tue, 21 Apr 2015 01:52:14 +0000 (09:52 +0800)
commit28dde1e38f96f47932c0d27dfa2d3bec4d7c5384
tree4fa3fe18d03592c2da40930f40b753c278b3114d
parentb8bbaaef3abb6c8dd4f768c51684f3ad97173b07
fhdl/verilog: add flag to produce ASIC-friendly output
migen/fhdl/verilog.py