Add abc9_required to DSP48E1.{A,B,C,D,PCIN}
authorEddie Hung <eddie@fpgeh.com>
Sat, 11 Jan 2020 01:12:31 +0000 (17:12 -0800)
committerEddie Hung <eddie@fpgeh.com>
Sat, 11 Jan 2020 01:12:31 +0000 (17:12 -0800)
commit28f814ee59e36230200108381a9c674c5275e3e4
tree1e39288025f594d95de607d9b8360598914d93a2
parent475d983676a42e57a104aaf5e72462d704c0c3aa
Add abc9_required to DSP48E1.{A,B,C,D,PCIN}
techlibs/xilinx/cells_sim.v