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(parent: 5ee5dfd) | patch
i965: Set MaxCombinedUniformBlocks properly.
authorKenneth Graunke <kenneth@whitecape.org>
Fri, 13 Nov 2015 22:55:50 +0000 (14:55 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Tue, 17 Nov 2015 00:24:44 +0000 (16:24 -0800)
commit292df1940126f267418e656b9ec33eb3f06667b8
tree33be942aa9341d5e868780bc463cb350f685d41dtree
parent5ee5dfddeafde2e2b89f86d2a59769a61ce5d6b2commit | diff
i965: Set MaxCombinedUniformBlocks properly.

Up until now, we've been letting core Mesa initialize it to 36 for us
(which is presumably BRW_MAX_UBO (12) * (VS+GS+FS stages -> 3)).

With compute and tessellation, we need to increase this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
src/mesa/drivers/dri/i965/brw_context.c diff | blob | history