anv: Emit CS Stall before Instruction Cache flush for gen12 WA
authorJordan Justen <jordan.l.justen@intel.com>
Thu, 16 Jan 2020 21:16:24 +0000 (13:16 -0800)
committerMarge Bot <eric+marge@anholt.net>
Tue, 28 Jan 2020 21:57:17 +0000 (21:57 +0000)
commit2969012d03be1b0690eed6a855ffc57535c721eb
tree86c6a10e056957f302078fbaa3f376c2d2ec2ce6
parentda03e07cc2f09b451705eeadfb24a12a640f6961
anv: Emit CS Stall before Instruction Cache flush for gen12 WA

Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Rework: Merge with other anvil pre-invalidate stalls (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
src/intel/vulkan/genX_cmd_buffer.c