tests: add an generate-else test too
authorEddie Hung <eddie@fpgeh.com>
Mon, 11 May 2020 17:26:08 +0000 (10:26 -0700)
committerEddie Hung <eddie@fpgeh.com>
Mon, 25 May 2020 14:36:53 +0000 (07:36 -0700)
commit29d84339bf9ec8f1d2be3fa20f81843f3ee08324
tree476433f7676b6cb933d62c88d93dda01e1489e20
parent88bddb37c91e8fe136e5c9cc2ade20fadccd1946
tests: add an generate-else test too
tests/verilog/bug2037.ys