Merge pull request #670 from rubund/feature/basic_svinterface_test
authorClifford Wolf <clifford@clifford.at>
Fri, 19 Oct 2018 11:03:38 +0000 (13:03 +0200)
committerGitHub <noreply@github.com>
Fri, 19 Oct 2018 11:03:38 +0000 (13:03 +0200)
commit2a104b29fd7e504bdedb27c286cf9125d46dfd55
tree9a0ef937b730d4c0f7452b0ceedfb642c83908ab
parenta25f370191707def4d50dd42e74dec4d097a6a22
parentd5aac2650f9169b2b890854083c5502b84adf115
Merge pull request #670 from rubund/feature/basic_svinterface_test

Basic test for checking correct synthesis of SystemVerilog interfaces