Port: Add protocol-agnostic ports in the port hierarchy
authorAndreas Hansson <andreas.hansson@arm.com>
Mon, 15 Oct 2012 12:12:35 +0000 (08:12 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Mon, 15 Oct 2012 12:12:35 +0000 (08:12 -0400)
commit2a740aa09682c32eb8f1f8880f279c943d8c6ee1
tree61ca1dcb9336bc1f4dbc791c876875c1c260ca8d
parent9baa35ba802f2cfb9fb9ecdebf111f4cd793a428
Port: Add protocol-agnostic ports in the port hierarchy

This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.

The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
53 files changed:
src/arch/arm/table_walker.cc
src/arch/arm/table_walker.hh
src/arch/arm/tlb.cc
src/arch/arm/tlb.hh
src/arch/x86/interrupts.hh
src/arch/x86/pagetable_walker.cc
src/arch/x86/pagetable_walker.hh
src/arch/x86/tlb.cc
src/arch/x86/tlb.hh
src/cpu/base.cc
src/cpu/base.hh
src/cpu/testers/directedtest/RubyDirectedTester.cc
src/cpu/testers/directedtest/RubyDirectedTester.hh
src/cpu/testers/memtest/memtest.cc
src/cpu/testers/memtest/memtest.hh
src/cpu/testers/networktest/networktest.cc
src/cpu/testers/networktest/networktest.hh
src/cpu/testers/rubytest/RubyTester.cc
src/cpu/testers/rubytest/RubyTester.hh
src/cpu/testers/traffic_gen/traffic_gen.cc
src/cpu/testers/traffic_gen/traffic_gen.hh
src/dev/copy_engine.cc
src/dev/copy_engine.hh
src/dev/dma_device.cc
src/dev/dma_device.hh
src/dev/io_device.cc
src/dev/io_device.hh
src/dev/pcidev.hh
src/dev/x86/i82094aa.hh
src/mem/addr_mapper.cc
src/mem/addr_mapper.hh
src/mem/bridge.cc
src/mem/bridge.hh
src/mem/bus.cc
src/mem/bus.hh
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/comm_monitor.cc
src/mem/comm_monitor.hh
src/mem/mem_object.cc
src/mem/mem_object.hh
src/mem/port.cc
src/mem/port.hh
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/RubyPort.hh
src/mem/simple_dram.cc
src/mem/simple_dram.hh
src/mem/simple_mem.cc
src/mem/simple_mem.hh
src/python/swig/pyobject.cc
src/sim/system.cc
src/sim/system.hh
src/sim/tlb.hh