Bugfix in write_verilog for RTLIL processes
authorClifford Wolf <clifford@clifford.at>
Mon, 14 Mar 2016 12:03:28 +0000 (13:03 +0100)
committerClifford Wolf <clifford@clifford.at>
Mon, 14 Mar 2016 12:03:28 +0000 (13:03 +0100)
commit2a8d5e64f5a994fa8f4f51c00d647ad977e42e4b
treece680097440c4b00c8bb8d7888d7d7fbb1f2550c
parentdac807fb33a3619dea955ce4b16342e6e0008111
Bugfix in write_verilog for RTLIL processes
backends/verilog/verilog_backend.cc