misc: Add explicit overrides and fix other clang >= 3.5 issues
authorAndreas Hansson <andreas.hansson@arm.com>
Mon, 12 Oct 2015 08:08:01 +0000 (04:08 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Mon, 12 Oct 2015 08:08:01 +0000 (04:08 -0400)
commit2ac04c11accb46f92cf7f2b7abe40404dbf8c5d6
tree368b579a0b45840a5248fca568f89a8ea7ca9d49
parent22c04190c607b9360d9a23548f8a54e83cf0e74a
misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
58 files changed:
src/arch/alpha/process.hh
src/arch/alpha/system.hh
src/arch/alpha/tlb.hh
src/arch/arm/table_walker.hh
src/arch/arm/tlb.hh
src/arch/generic/tlb.hh
src/cpu/base.hh
src/cpu/checker/cpu.hh
src/cpu/minor/cpu.hh
src/cpu/minor/func_unit.cc
src/cpu/minor/pipeline.hh
src/cpu/o3/cpu.hh
src/cpu/pred/bpred_unit.hh
src/cpu/simple/atomic.hh
src/cpu/simple/base.hh
src/cpu/simple/timing.hh
src/cpu/testers/traffic_gen/traffic_gen.hh
src/dev/alpha/backdoor.hh
src/dev/alpha/tsunami.hh
src/dev/alpha/tsunami_cchip.hh
src/dev/alpha/tsunami_io.hh
src/dev/alpha/tsunami_pchip.hh
src/dev/copy_engine.hh
src/dev/disk_image.hh
src/dev/dma_device.hh
src/dev/etherlink.hh
src/dev/ethertap.hh
src/dev/i2cbus.hh
src/dev/i8254xGBe.hh
src/dev/ide_ctrl.hh
src/dev/ide_disk.hh
src/dev/ns_gige.hh
src/dev/pcidev.hh
src/dev/sinic.hh
src/dev/uart8250.hh
src/dev/virtio/fs9p.hh
src/mem/abstract_mem.hh
src/mem/cache/cache.hh
src/mem/cache/tags/base_set_assoc.hh
src/mem/cache/tags/fa_lru.hh
src/mem/dram_ctrl.hh
src/mem/dramsim2.hh
src/mem/page_table.hh
src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
src/mem/ruby/structures/RubyMemoryControl.hh
src/mem/ruby/system/DMASequencer.hh
src/mem/ruby/system/RubyPort.hh
src/mem/ruby/system/RubySystem.hh
src/mem/simple_mem.hh
src/sim/clock_domain.hh
src/sim/process.hh
src/sim/root.hh
src/sim/sim_events.hh
src/sim/system.hh
src/sim/ticked_object.hh
src/sim/voltage_domain.hh