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(parent: 1f083d1) | patch
reduce jtag data bus width to 32, to match litex
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 8 Apr 2021 20:31:05 +0000 (21:31 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 8 Apr 2021 20:31:05 +0000 (21:31 +0100)
commit2af6d3f17c328d07719661106729f63c626e693a
tree6bb37ff94816f93dc01fca66995bd8c08ecf31actree
parent1f083d172b74de119dd1524aee00323885a74fc2commit | diff
reduce jtag data bus width to 32, to match litex
set (ignored) pc_i to 64 bit
remove mem_2.init cp
Makefile diff | blob | history
libresoc/core.py diff | blob | history