| author | whitequark <whitequark@whitequark.org> | |
| Fri, 21 Dec 2018 01:55:59 +0000 (01:55 +0000) | ||
| committer | whitequark <whitequark@whitequark.org> | |
| Fri, 21 Dec 2018 01:55:59 +0000 (01:55 +0000) | ||
| commit | 2b4a8510ca3653e796b0a6f8ac0d7868cfdf9a9b | |
| tree | c21f79228964f9d84e0a6c7afbb1f2d1dd5c0bea | tree |
| parent | 6d9a6b5d84b7b5bc01e76a74ecf9148649945393 | commit | diff |
| examples/mem.py | [new file with mode: 0644] | blob |
| nmigen/back/rtlil.py | diff | blob | history | |
| nmigen/back/verilog.py | diff | blob | history |