back.rtlil: implement memories.
authorwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 01:55:59 +0000 (01:55 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 01:55:59 +0000 (01:55 +0000)
commit2b4a8510ca3653e796b0a6f8ac0d7868cfdf9a9b
treec21f79228964f9d84e0a6c7afbb1f2d1dd5c0bea
parent6d9a6b5d84b7b5bc01e76a74ecf9148649945393
back.rtlil: implement memories.
examples/mem.py [new file with mode: 0644]
nmigen/back/rtlil.py
nmigen/back/verilog.py