opcodes/riscv-dis.c: Tidying with comments/clarity
authorTsukasa OI <research_trasio@irq.a4lg.com>
Sat, 27 Aug 2022 13:07:05 +0000 (13:07 +0000)
committerTsukasa OI <research_trasio@irq.a4lg.com>
Fri, 14 Oct 2022 05:21:41 +0000 (05:21 +0000)
commit2b8fd83908ea61d9fb2215de5eb585870658fa89
tree73966e336f94455bce3fb1448bf25b493d167576
parent58eb738fed378626e4b0b0cef26fdc5013750d04
opcodes/riscv-dis.c: Tidying with comments/clarity

Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.

First, we need to clarify the roles of variables and code portions.

opcodes/ChangeLog:

* riscv-dis.c (xlen): Move before default_isa_spec. Add comment.
(default_isa_spec, default_priv_spec): Add comment.
(riscv_gpr_names, riscv_fpr_names): Likewise.
(parse_riscv_dis_option_without_args): Likewise.
(parse_riscv_dis_option, parse_riscv_dis_options): Likewise.
(maybe_print_address): Likewise.
(riscv_disassemble_insn): Fix comment about the Zfinx "extension".
Add comment about the riscv_multi_subset_supports call.
opcodes/riscv-dis.c