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(parent: c1d8300) | patch
i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS
authorAnuj Phogat <anuj.phogat@gmail.com>
Thu, 31 May 2018 23:03:44 +0000 (16:03 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Mon, 9 Jul 2018 22:38:42 +0000 (15:38 -0700)
commit2badf0e85b3a54119b08c559dc18aed43a156295
tree9226ec23b0f30aa7c067431678ee3ad914a4f881tree
parentc1d8300117891ec87762caa30d14307622c65bcfcommit | diff
i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS

CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
src/mesa/drivers/dri/i965/brw_state_upload.c diff | blob | history