add verilog backend to use the core with a "standard" flow
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 19 Jan 2015 17:40:32 +0000 (18:40 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 19 Jan 2015 19:38:48 +0000 (20:38 +0100)
commit2bb9c6b6496096f44a83a52c4c6c31e6eb4dadf6
tree3abe2986d563b133a34455320073a0753301f10d
parentd84ae7c80c4992329ecb871fbaf94e470424323b
add verilog backend to use the core with a "standard" flow
litesata/phy/__init__.py
make.py
platforms/kc705.py
platforms/verilog_backend.py [new file with mode: 0644]
targets/bist.py
targets/core.py [new file with mode: 0644]