radeonsi: add support for displayable DCC for 1 RB chips
authorMarek Olšák <marek.olsak@amd.com>
Sat, 5 Jan 2019 00:19:54 +0000 (19:19 -0500)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 4 Apr 2019 13:53:24 +0000 (09:53 -0400)
commit2c09eb41221eb704e9e7a21654828173158d1a7d
tree6adb48d0372e6dd5562080ef7740190414abb9a6
parent029bfa3d253ca70186e245ccf0a7e17bb40a5bab
radeonsi: add support for displayable DCC for 1 RB chips

This is the simpler codepath - just disable RB and pipe alignment for DCC.
src/amd/common/ac_gpu_info.c
src/amd/common/ac_gpu_info.h
src/amd/common/ac_surface.c
src/amd/common/ac_surface.h
src/gallium/drivers/radeon/radeon_winsys.h
src/gallium/drivers/radeonsi/si_texture.c
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c