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(parent: c0b68f4) | patch
Verilog backend for $mem cells should now be able to handle different
authorluke whittlesey <luke.whittlesey@gmail.com>
Fri, 8 May 2015 19:29:51 +0000 (15:29 -0400)
committerluke whittlesey <luke.whittlesey@gmail.com>
Fri, 8 May 2015 19:29:51 +0000 (15:29 -0400)
commit2c1e15029786fe8a118343b7a81f681450a8ce93
treed86ef62ae3c058a5b30697c08ca30dfdb6f25a7dtree
parentc0b68f4848f709034d68dbfa8697abe76b67a69ecommit | diff
Verilog backend for $mem cells should now be able to handle different
write-enable bits and RD_TRANSPARENT parameter settings.
backends/verilog/verilog_backend.cc diff | blob | history