[PATCH][AArch64] Fix missing optimization for CMP+AND
authorKyrylo Tkachov <kyrylo.tkachov@arm.com>
Thu, 27 Jul 2017 16:29:31 +0000 (16:29 +0000)
committerJames Greenhalgh <jgreenhalgh@gcc.gnu.org>
Thu, 27 Jul 2017 16:29:31 +0000 (16:29 +0000)
commit2c2789d582f8fcafd9ef46a22dcb5ca08c5eecd8
tree2c0f09817f8455203b1c9380e0f904f72c8cfb9c
parent06bd22f6099abe4fec73c988daf4cacd68f34329
[PATCH][AArch64] Fix missing optimization for CMP+AND

During combine GCC tries to merge CMP (with zero) and AND into a TST. However,
in cases where an ANDS operand is not compatible, this was being missed. Adding
a define_split where this operand was moved to a register seems to help out.

Committed on behalf of Sudi Das

---
gcc/

2017-07-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
    Sudakshina Das  <sudi.das@arm.com>

* config/aarch64/aarch64.md
(define_split for and<mode>3nr_compare): Move
non aarch64_logical_operand to a register.
(define_split for and_<SHIFT:optab><mode>3nr_compare0): Move non
register immediate operand to a register.
* config/aarch64/predicates.md (aarch64_mov_imm_operand): New.

gcc/testsuite

2017-07-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
    Sudakshina Das  <sudi.das@arm.com>

* gcc.target/aarch64/tst_imm_split_1.c: New Test.

Co-Authored-By: Sudakshina Das <sudi.das@arm.com>
From-SVN: r250631
gcc/ChangeLog
gcc/config/aarch64/aarch64.md
gcc/config/aarch64/predicates.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c [new file with mode: 0644]